Dr. REGINALD H. VANLALCHAKA

Assistant Professor | Department of Electronics | Government Zirtiri Residential Science College

Qualifications M.Tech (Electronics & Communication Engineering); Ph.D. (Mizoram University, awarded 25 July 2025); UGC-NET (Electronics Science)
Specialization Low-power VLSI, adiabatic/quasi-adiabatic logic, digital CMOS/FinFET circuits, embedded systems and IoT
Experience Assistant Professor, Department of Electronics, GZRSC, since 4 July 2018
Contact Mobile: 8974750040 | Email: rh73058@gmail.com

RESEARCH & INTELLECTUAL PROPERTY

Indian Patent No. 564217 (Granted; Inventor): “An Ultra-Low Power VLSI Circuit Design Technique.” Application No. 202131003952; filed 29 January 2021; granted 28 March 2025.

Research profile: Research in energy-efficient VLSI/adiabatic switching with peer-reviewed papers published by Springer Nature, Elsevier and IOP Publishing; additional IEEE conference papers.

JOURNAL PAPERS

  1. Architectural design of sequential circuit based on improved diode-free adiabatic logic. R. H. Vanlalchaka, R. Maity, R. L. Ralte, L. R. M. Punte, P. C. Rohmingliana, R. Lalawmpuii & N. P. Maity. Analog Integrated Circuits and Signal Processing, 124, Article 71 (2025). Publisher: Springer Nature. DOI: 10.1007/s10470-025-02463-4.
  2. A novel adiabatic logic technique for low-power circuit applications. R. H. Vanlalchaka, R. Maity, L. Khiangte, D. Rosangliana & N. P. Maity. Microsystem Technologies, 31(2), 611–630 (2025). Publisher: Springer Nature. DOI: 10.1007/s00542-024-05842-5.
  3. Energy-Efficient circuits with improved diode free adiabatic logic design methodology. R. H. Vanlalchaka, R. Maity & N. P. Maity. Ain Shams Engineering Journal, 14, Article 102049 (2023). Publisher: Elsevier. DOI: 10.1016/j.asej.2022.102049. 2025 Journal Impact Factor (JCR): 6.2.
  4. A low power design using FinFET based adiabatic switching principle: Application to 16-Bit arithmetic logic unit. R. H. Vanlalchaka, R. Maity & N. P. Maity. Ain Shams Engineering Journal, 14, Article 101948 (2023). Publisher: Elsevier. DOI: 10.1016/j.asej.2022.101948. 2025 Journal Impact Factor (JCR): 6.2.
  5. A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter. R. H. Vanlalchaka, R. Maity & N. P. Maity. Engineering Research Express, 5(1), Article 015058 (2023). Publisher: IOP Publishing. DOI: 10.1088/2631-8695/acae1b.
  6. 4-bit ripple carry adder using proposed energy efficient single phase adiabatic logic technique. S. Roy & R. H. Vanlalchaka. International Journal on Current Science and Technology, 1(2) (2013).
  7. Design & analysis of N-bit comparator based on low power adiabatic logic technique. S. Roy & R. H. Vanlalchaka. International Journal on Current Science and Technology, 1(2) (2013).
  8. Acetylcholine gated spiking neuron model. S. Roy, M. Boro, J. C. Dutta & R. H. Vanlalchaka. International Journal on Current Science and Technology, 1(1) (2013).
  9. Power efficient adiabatic gray to binary and binary to gray code converter circuits. S. Roy & R. H. Vanlalchaka. International Journal on Current Science and Technology, 1(1) (2013).

CONFERENCE PAPERS / PROCEEDINGS

  1. “Correlation analysis between drowsiness and heart rate variability parameters” — Mizoram Science Congress 2018, Advances in Engineering Research, 178, 47–51. DOI: 10.2991/msc-18.2018.8. Publisher: Atlantis Press
  2. “Power efficient priority encoder and decoder” — ICCCI 2014, Coimbatore, India. DOI: 10.1109/ICCCI.2014.6921806. Publisher: IEEE
  3. “Adiabatic logic based low power multiplexer and demultiplexer” — ICCCI 2014, Coimbatore, India. DOI: 10.1109/ICCCI.2014.6921808. Publisher: IEEE
  4. “Power efficient odd parity generator & checker circuits” — ICETACS 2013, Shillong, Meghalaya. DOI: 10.1109/ICETACS.2013.6691397. Publisher: IEEE

OTHER CONFERENCE PRESENTATIONS & ACADEMIC EVENTS

  1. “A New Combinational Circuit Approach Using Improved Diode Free Adiabatic Logic Families,” 6th International Conference on Energy Systems, Drives and Automations (ESDA 2023); abstract record.
  2. “Power Efficient 8421 Code to Excess-3 Code Converter: A New Circuit Design Approach,” ICRTECS 2019 (listed as accepted in earlier GZRSC profile; final proceedings not confirmed).
  3. “Acetylcholine Gated Spiking Neuron Model” and “Power Efficient Adiabatic Gray to Binary and Binary to Gray Code Converter Circuits,” North Eastern Region Science Congress (2013).

AWARDS, MENTORSHIP & PROFESSIONAL RESPONSIBILITIES

  • Jury Member (Electronics): LESDE, Government of Mizoram, for IndiaSkills-related skill competitions (2023–2024; 2025–2026); District/State Jury appointment in 2025.
  • IndiaSkills mentees: Shri Lalremsiama — Regional Gold Medal (2025–2026), subsequently represented Mizoram at National IndiaSkills; Shri Lalmuansanga — Regional Medallion for Excellence (2025–2026).
  • Mentored a student project winning First Prize, Higher & Technical Hardware Category, Chief Minister’s Inventor Challenge / Bana Kaih, Mizoram (27 March 2025).
  • Received GZRSC appreciation for technical initiatives and IoT/electronics project demonstrations supporting institutional activities and NAAC peer-team visit.
  • Institutional mentor, Smart India Hackathon 2026; Mizoram University UG Electronics paper setter and examiner (2025–2026).

INNOVATION & TECHNICAL CONTRIBUTIONS

Practical development and mentoring in ESP8266/ESP32-based embedded systems, sensors and IoT, electronic control and display systems, automation, remote alerts and energy-efficient circuits. College initiatives include smart dustbin, automatic sanitizer dispenser and energy-saving LED bulb circuitry.

TRAINING, SEMINARS & WORKSHOPS

National Workshop on Electronic Devices (Mizoram University / IEEE-EDS, 2011); National Workshop on Advances in Electronics, Communication & Information Technology (AECI 2011); DIgSILENT PowerFactory Workshop (2015); Seminar on Intellectual Property Rights (GZRSC / MISTIC, 2025).

ACADEMIC PROFILE

ResearchGate: https://www.researchgate.net/profile/Reginald-Vanlalchaka

This page was updated on 19th  Oct 2026

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